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HIP4086, HIP4086A
General PCB Layout Guidelines
The AC performance of the HIP4086/A depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance:
? Place the driver as close as possible to the driven power FETs.
? Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
? Keep power loops as short as possible by paralleling the
source and return traces.
? Use planes where practical; they are usually more effective
than parallel traces.
? Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
? When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10k ? resistor, is
10x larger than the noise on a 1k ? resistor.
? Be aware of magnetic fields emanating from motors,
transformers and inductors. Gaps in these magnetic structures
are especially bad for emitting flux.
? If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
? The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
? Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
13
? It may be necessary to add resistance to dampen resonating
parasitic circuits especially on xHO and xLO. If an external gate
resistor is unacceptable, then the layout must be improved to
minimize lead inductance.
? Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the HIP4086/A.
? Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
? Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
? Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated. This must be accounted for in the PCB
layout and circuit design.
? If you simulate your circuits, consider including parasitic
components especially parasitic lead inductance.
FN4220.9
February 1, 2013
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